Document
TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS
D Based Upon the T320C2xLP Core CPU
D 16-Bit Fixed-Point DSP Architecture
– Six Internal Buses for Increased
Parallelism and Performance
– 32-Bit ALU/Accumulator
– 16 × 16-Bit Single-Cycle Multiplier With a
32-Bit Product
– Block Moves for Data, Program,
I/O Space
– Hardware Repeat Instruction
D Instruction Cycle Time
’C203
’LC203
’C209
50 ns @ 5 V 50 ns @ 3.3 V 50 ns @ 5 V
35 ns @ 5 V
35 ns @ 5 V
25 ns @ 5 V
D Source Code Compatible With TMS320C25
D Upwardly Code-Compatible With
TMS320C5x Devices
D Four External Interrupts
D Boot-Loader Option (’C203 Only)
D TMS320C2xx Integrated Memory:
– 544 × 16 Words of On-Chip Dual-Access
Data RAM
– 4K × 16 Words of On-Chip Single-Access
Program/Data RAM (’C209 only)
– 4K × 16 Words of On-Chip Program ROM
(’C209 Only)
D 224K × 16-Bit Total Addressable External
Memory Space
– 64K Program
– 64K Data
– 64K I/O
– 32K Global
SPRS025B – JUNE 1995 – REVISED AUGUST 1998
D TMS320C2xx Peripherals:
– PLL With Various Clock Options
– ×1, ×2, ×4, 2 (’C203) – ×2, 2 (’C209)
– On-Chip Oscillator
– One Wait State Software-Programmable
to Each Space (’C209 Only)
– 0 – 7 Wait States Software-Programmable
to Each Space (’C203 Only)
– Six General-Purpose I/O Pins
– On-Chip 20-Bit Timer
– Full-Duplex Asynchronous Serial Port
(UART) (’C203 Only)
– One Synchronous Serial Port With
Four-Level-Deep FIFOs (’C203 Only)
D Supports Hardware Wait States D Designed for Low-Power Consumption
– Fully Static CMOS Technology
– Power-Down IDLE Mode
D 1.1 mA/MIPS at 3.3 V D ’C203 is Pin-Compatible With TMS320F206
Flash DSP
D Up to 40-MIPS Performance at 5 V (’C203) D 20-MIPS Performance at 3.3 V D HOLD Mode for Multiprocessor
Applications
D IEEE-1149.1†-Compatible Scan-Based
Emulation
D 80- and 100-pin Small Thin Quad Flat
Packages (TQFPs), (PN and PZ Suffixes)
description
The TMS320C2xx generation of digital signal processors (DSPs) combines strong performance and great flexibility to meet the needs of signal processing and control applications. The T320C2xLP core CPU that is the basis of all ’C2xx devices has been optimized for high speed, small size, and low-power, making it ideal for demanding applications in many markets. The CPU has an advanced, modified Harvard architecture with six internal buses that permits tremendous parallelism and data throughput. The powerful ’C2xx instruction set makes software development easy. And because the ’C2xx is code-compatible with the TMS320C2x and ’C5x generations, your code investment is preserved. Around this core, ’C2xx-generation devices feature various combinations of on-chip memory and peripherals. The serial ports provide easy communication with external devices such as codecs, A/D converters, and other processors. Other peripherals that facilitate the control of external devices include general-purpose I/O pins, a 20-bit timer, and a wait-state generator.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS
SPRS025B – JUNE 1995 – REVISED AUGUST 1998
description (continued)
Because of their strong performance, low cost, and easy-to-use development environment, ’C2xx-generation DSPs are an ideal choice for applications such as smart phones, digital cameras, modems, remote metering, and security systems.
PZ PACKAGE (TOP VIEW)
PN PACKAGE (TOP VIEW)
VDD A15 A14 A13 A12 VSS A11 A10 A9 A8 VSS A7 VDD A6 A5 A4 VSS A3 A2 A1 A0 VSS PS IS DS 80 TRST 79 IACK 78 RD 77 CLKOUT1 76 VDD 75 XF 74 CLKMOD 73 VSS 72 TOUT 71 TDO 70 X1 69 CLKIN/X2 68 BR 67 STRB 66 R / W 65 PS 64 IS 63 DS 62 WE 61 VSS
EMU0 EMU1/OFF
TCK TRST
TDI TMS TDO VSS CLKR FSR
DR CLKX
VSS FSX DX VDD TOUT
TX VSS RX IO0 IO1
XF BIO RS
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
79
47
80
46
81
45
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44
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43
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42
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41
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40
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90
36
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35
92
34
93
33
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32
95
31
96
30
97
29
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDD READY
VSS R/W
STRB
VDD 1 EMU0 2
RD EMU1/OFF 3
WE
RS 4
BR
TDI 5
VSS
RS 6
D15
READY 7
D14
TCK 8
D13
BIO 9
D12
MP/MC 10
VSS
D15 11
D11
VSS 12
VDD
D14 13
D10
D13 14
D9
VDD 1.