TMS320LC203

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS D Based Upon the T320C2xLP Core CPU D 16-Bit Fixed-Point DSP Architecture – Six Internal Buses for Increased Parallelism and Performance – 32-Bit ALU/Accumulator – 16 × 16-Bit Single-Cycle Multiplier With a 32-Bit Product – Block Moves for Data, Program, I/O Space – Hardware Repeat Instruction D Instruction Cycle Time ’C203 ’LC203 ’C209 50 ns @ 5 V 50 ns @ 3.3 V 50 ns @ 5 V 35 ns @ 5 V 35 ns @ 5 V 25 ns @ 5 V D Source Code Compatible With TMS320C25 D Upwardly Code-Compatible With TMS320C5x Devices D Four External Interrupts D Boot-Loader Option (’C203 Only) D TMS320C2xx Integrated Memory: – 544 × 16 Words of On-Chip Dual-Access Data RAM – 4K × 16 Words of On-Chip Single-Access Program/Data RAM (’C209 only) – 4K × 16 Words of On-Chip Program ROM (’C209 Only) D 224K × 16-Bit Total Addressable External Memory Space – 64K Program – 64K Data – 64K I/O – 32K Global SPRS025B – JUNE 1995 – REVISED AUGUST 1998 D TMS320C2xx Peripherals: – PLL With Various Clock Options – ×1, ×2, ×4, 2 (’C203) – ×2, 2 (’C209) – On-Chip Oscillator – One Wait State Software-Programmable to Each Space (’C209 Only) – 0 – 7 Wait States Software-Programmable to Each Space (’C203 Only) – Six General-Purpose I/O Pins – On-Chip 20-Bit Timer – Full-Duplex Asynchronous Serial Port (UART) (’C203 Only) – One Synchronous Serial Port With Four-Level-Deep FIFOs (’C203 Only) D Supports Hardware Wait States D Designed f...