TMS320C6201

D High-Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6201 -- 5-ns Instruction Cycle Time -- 200-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1600 MIPS D VelociTI™ Advanced Very Long Instruction Word (VLIW) TMS320C62x™ DSP CPU Core -- Eight Independent Functional Units: -- Six ALUs (32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Results) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional D Instruction Set Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel D 16-Bit Host-Port Interface (HPI) -- Access to Entire Memory Map TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 GJC/GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGES (BOTTOM VIEW) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 D...