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TMS320C6202 Dataheets PDF



Part Number TMS320C6202
Manufacturers Texas Instruments
Logo Texas Instruments
Description FIXED-POINT DIGITAL SIGNAL PROCESSORS
Datasheet TMS320C6202 DatasheetTMS320C6202 Datasheet (PDF)

TMS320C6202, TMS320C6202B FIXED-POINT DIGITAL SIGNAL PROCESSORS D High-Performance Fixed-Point Digital Signal Processors (DSPs) -- TMS320C62x™ -- 5-, 4-, 3.33-ns Instruction Cycle Time -- 200-, 250-, 300-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1600, 2000, 2400 MIPS D C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package† D C6202B and C6203B GNZ and GNY Packages are Pin-Compatible D VelociTI™ Advanced Very-Long-Instruction- Word (VLIW).

  TMS320C6202   TMS320C6202


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TMS320C6202, TMS320C6202B FIXED-POINT DIGITAL SIGNAL PROCESSORS D High-Performance Fixed-Point Digital Signal Processors (DSPs) -- TMS320C62x™ -- 5-, 4-, 3.33-ns Instruction Cycle Time -- 200-, 250-, 300-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1600, 2000, 2400 MIPS D C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package† D C6202B and C6203B GNZ and GNY Packages are Pin-Compatible D VelociTI™ Advanced Very-Long-Instruction- Word (VLIW) C62x™ DSP Core -- Eight Highly Independent Functional Units: -- Six ALUs (32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Result) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional D Instruction Set Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 3M-Bit On-Chip SRAM -- 2M-Bit Internal Program/Cache (64K 32-Bit Instructions) -- 1M-Bit Dual-Access Internal Data (128K Bytes) -- Organized as Two 64K-Byte Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Synchronous Memories: SDRAM or SBSRAM -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- 52M-Byte Addressable External Memory Space SPRS104I -- OCTOBER 1999 -- REVISED MARCH 2004 D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D Flexible Phase-Locked-Loop (PLL) Clock Generator D 32-Bit Expansion Bus (XBus) -- Glueless/Low-Glue Interface to Popular PCI Bridge Chips -- Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses -- Master/Slave Functionality -- Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals D Three Multichannel Buffered Serial Ports (McBSPs) -- Direct Interface to T1/E1, MVIP, SCSA Framers -- ST-Bus-Switching Compatible -- Up to 256 Channels Each -- AC97-Compatible -- Serial-Peripheral Interface (SPI) Compatible (Motorola™) D Two 32-Bit General-Purpose Timers D IEEE-1149.1 (JTAG‡) Boundary-Scan-Compatible D 352-Pin BGA Package (GJL) (C6202) D 352-Pin BGA Package (GNZ) (C6202B) D 384-Pin BGA Package (GLS) (C6202) D 384-Pin BGA Package (GNY) (C6202B) D 0.18-μm/5-Level Metal Process (C6202) 0.15-μm/5-Level Metal Process (C6202B) -- CMOS Technology D 3.3-V I/Os, 1.8-V Internal (C6202) 3.3-V I/Os, 1.5-V Internal (C6202B) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. Other trademarks are the property of their respective owners. † For more details, see the GLS BGA package bottom view. ‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443 1 TMS320C6202, TMS320C6202B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS104I -- OCTOBER 1999 -- REVISED MARCH 2004 Table of Contents GJL, GNZ, GLS, and GNY BGA packages . . . . . . . . . . . . 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 C62x device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional and CPU (DSP core) block diagram . . . . . . . . . 9 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . 10 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . 13 parameter measurement information . . . . . . . . . . . . . . . 47 signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . 47 timing parameters and board routing analysis . . . . . . 48 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 52 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 56 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . 59 DMA synchronization events . . . . . . . . . . . . . . . . . . . . . . . 18 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 interrupt sources and interrupt selector . . . . . . . . . . . . . . 19 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 20 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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