TMS320C6203B

D High-Performance Fixed-Point Digital Signal Processor (DSP) − TMS320C62x − 4-, 3.33-ns Instruction Cycle Time − 250-, 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 2000, 2400 MIPS D C6203B and C6202 GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package† D C6203B and C6202B GNZ, GNY and ZNY Packages are Pin-Compatible D VelociTI Advanced Very-Long-Instruction- Word (VLIW) C62x DSP Core − Eight Highly Independent Functional Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Result) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D 7M-Bit On-Chip SRAM − 3M-Bit Internal Program/Cache (96K 32-Bit Instructions) − 4M-Bit Dual-Access Internal Data (512K Bytes) − Organized as Two 256K-Byte Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) − Glueless Interface to Synchronous Memories: SDRAM or SBSRAM − Glueless Interface to Asynchronous Memories: SRAM and EPROM − 52M-Byte Addressable External Memory Space TMS320C6203B FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS086N − JANUARY 1999 − REVISED JULY 2006 D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D Flexible Phase-Locked-Loop (PLL) Clock Generator D 32-Bit ...