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TMS320C6205 Dataheets PDF



Part Number TMS320C6205
Manufacturers Texas Instruments
Logo Texas Instruments
Description FIXED-POINT DIGITAL SIGNAL PROCESSOR
Datasheet TMS320C6205 DatasheetTMS320C6205 Datasheet (PDF)

D High-Performance Fixed-Point Digital Signal Processor (DSP) − TMS320C6205 − 5-ns Instruction Cycle Time − 200-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600 MIPS D VelociTI Advanced-Very-Long-Instruction- Word (VLIW) TMS320C62x DSP Core − Eight Highly Independent Functional Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Result) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D .

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D High-Performance Fixed-Point Digital Signal Processor (DSP) − TMS320C6205 − 5-ns Instruction Cycle Time − 200-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600 MIPS D VelociTI Advanced-Very-Long-Instruction- Word (VLIW) TMS320C62x DSP Core − Eight Highly Independent Functional Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Result) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D 1M-Bit On-Chip SRAM − 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) − 512K-Bit Dual-Access Internal Data (64K Bytes) − Organized as Two 32K-Byte Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) − Glueless Interface to Synchronous Memories: SDRAM or SBSRAM − Glueless Interface to Asynchronous Memories: SRAM and EPROM − 52M-Byte Addressable External Memory Space D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D Flexible Phase-Locked-Loop (PLL) Clock Generator TMS320C6205 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS106G − OCTOBER 1999 − REVISED JULY 2006 D 32-Bit/33-MHz Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to: PCI Specification 2.2 Power Management Interface 1.1 Meets Requirements of PC99 − PCI Access to All On-Chip RAM, Peripherals, and External Memory (via EMIF) − Four 8-Deep x 32-Wide FIFOs for Efficient PCI Bus Data Transfer − 3.3/5-V PCI Operation − Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O − Supports 4-Wire Serial EEPROM Interface − PCI Interrupt Request Under DSP Program Control − DSP Interrupt Via PCI I/O Cycle D Two Multichannel Buffered Serial Ports (McBSPs) − Direct Interface to T1/E1, MVIP, SCSA Framers − ST-Bus-Switching Compatible − Up to 256 Channels Each − AC97-Compatible − Serial-Peripheral-Interface (SPI) Compatible (Motorola) D Two 32-Bit General-Purpose Timers D IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible D 288-Pin MicroStar BGA Package (GHK and ZHK Suffixes) D 0.15-µm/5-Level Metal Process − CMOS Technology D 3.3-V I/Os, 1.5-V Internal, 5-V Voltage Tolerance for PCI I/O Pins Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2006, Texas Instruments Incorporated • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 1 TMS320C6205 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS106G − OCTOBER 1999 − REVISED JULY 2006 Table of Contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 GHK and ZHK BGA packages (bottom view) . . . . . . . . . . 4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional and CPU (DSP core) block diagram . . . . . . . . . 7 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . 8 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 11 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 recommended operating conditions . . . . . . . . . . . . . . . . . 33 recommended operating conditions (PCI only) . . . . . . . . 33 electrical characteristics over recommended rangesof supply voltage and operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 electrical characteristics over recommended ranges of supply voltage and operating case temperature (PCI only) . . . . . . . . . . . .


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