Fixed-Point Digital Signal Processor
TMS320C6411 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS196I − MARCH 2002 − REVISED JUNE 2005
D Low-Cost, High-Performanc...
Description
TMS320C6411 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS196I − MARCH 2002 − REVISED JUNE 2005
D Low-Cost, High-Performance Fixed-Point
DSP − TMS320C6411 − 3.33-ns Instruction Cycle Time − 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − Twenty-Eight Operations/Cycle − 2400 MIPS − Fully Software-Compatible With
TMS320C62x
D VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core − Eight Highly Independent Functional
Units With VelociTI.2 Extensions: − Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle − Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle − Non-Aligned Load-Store Architecture − 64 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional
D Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − VelociTI.2 Increased Orthogonality
D L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
− 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM...
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