TMS320C6657

Product Folder Order Now Technical Documents Tools & Software Support & Community TMS320C6655, TMS320C6657 SPRS814D – MARCH 2012 – REVISED OCTOBER 2019 TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor 1 Device Overview 1.1 Features 1 One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With – 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core – 40 GMAC per Core for Fixed Point @ 1.25 GHz – 20 GFLOP per Core for Floating Point @ 1.25 GHz Multicore Shared Memory Controller (MSMC) – 1024KB MSM SRAM Memory (Shared by Two DSP C66x CorePacs for C6657) – Memory Protection Unit for Both MSM SRAM and DDR3_EMIF Multicore Navigator – 8192 Multipurpose Hardware Queues with Queue Manager – Packet-Based DMA for Zero-Overhead Transfers Hardware Accelerators – Two Viterbi Coprocessors – One Turbo Coprocessor Decoder Peripherals – Four Lanes of SRIO 2.1 – 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane – Supports Direct I/O, Message Passing – Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations – PCIe Gen2 – Single Port Supporting 1 or 2 Lanes – Supports up to 5 GBaud Per Lane – HyperLink – Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability – Supports up to 40 Gbaud – Gigabit Ethernet (GbE) Subsystem – One SGMII Port – Supports 10-, 100-, and 1000-Mbps Operation – 32-Bit DDR3 Interface – DDR3-1333 – 4GB of Addressable Mem...