TMS320C6670

TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS689D March 2012 TMS320C6670 Data Manual SPRS689D—March 2012 Release History www.ti.com Revision Date D March 2012 C October 2011 B August 2011 A April 2011 SPRS689 February 2011 Description/Comments Updated PASS PLL section (block diagram, PASS PLL Control Register, and initialization sequence) Updated Switch Fabric Matrix tables with bridge numbers and added Switch Fabric block diagrams Updated the JTAGID register table Restricted Output_Divide of SECCTL to max value of divide by 2 Changed TPTCn to EDMA3TCn and TPCCn to EDMA3CCn throughout the data manual Replaced all INTC with CIC and CPT with Tracer throughout the document Updated main PLL lock time Added DDR3PLL and PASS PLL Reset bits in DDR3PLLCTL1 and PASSPLLCTL1 registers Added the DDR3PLL and PASSPLL Initialization Sequence Added po_vcon_smpserr_intr SmartReflex event Corrected the SPI and DDR3/Hyperbridge Config Memory Map end address Added DEVSPEED Register section Removed Parameter Information section from chapter 7 as the content was not relevant Added more description to Boot Sequence section Changed all footnote references from CORECLK to SYSCLK1 Corrected the typo in the addre...