TMS320C6672

TMS320C6672 SPRS708E—November 2010—Revised March 2014 Multicore Fixed and Floating-Point Digital Signal Processor Check for Evaluation Modules (EVM): TMS320C6678 1 TMS320C6672 Features and Description 1.1 Features Two TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Each with – 1.0 GHz, 1.25 GHz, or 1.5 GHz C66x Fixed/Floating-Point CPU Core › 48 GMAC/Core for Fixed Point @ 1.5 GHz › 24 GFLOP/Core for Floating Point @ 1.5 GHz – Memory › 32K Byte L1P Per Core › 32K Byte L1D Per Core › 512K Byte Local L2 Per Core Multicore Shared Memory Controller (MSMC) – 4096KB MSM SRAM Memory Shared by Two DSP C66x CorePacs – Memory Protection Unit for Both MSM SRAM and DDR3_EMIF Multicore Navigator – 8192 Multipurpose Hardware Queues with Queue Manager – Packet-Based DMA for Zero-Overhead Transfers Network Coprocessor – Packet Accelerator Enables Support for › Transport Plane IPsec, GTP-U, SCTP, PDCP › L2 User Plane PDCP (RoHC, Air Ciphering) › 1-Gbps Wire-Speed Throughput at 1.5 MPackets Per Second – Security Accelerator Engine Enables Support for › IPSec, SRTP, 3GPP, WiMAX Air Interface, and SSL/TLS Security › ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5 › Up to 2.8 Gbps Encryption Speed Peripherals – Four Lanes of SRIO 2.1 › 1.24/2.5/3.125/5 GBaud Operation Supported Per Lane › Supports Direct I/O, Message Passing › Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations – PCIe Gen2 ...