TMS320C6711D

TMS320C6711D FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR D Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP): TMS320C6711D − Eight 32-Bit Instructions/Cycle − 167-, 200-, 250-MHz Clock Rates − 6-, 5-, 4-ns Instruction Cycle Time − 1000, 1200, 1500 MFLOPS D Advanced Very Long Instruction Word (VLIW) C67x DSP Core − Eight Highly Independent Functional Units: − Four ALUs (Floating- and Fixed-Point) − Two ALUs (Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Hardware Support for IEEE Single-Precision and Double-Precision Instructions − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D L1/L2 Memory Architecture − 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) − 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) − 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) D Device Configuration − Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot − Endianness: Little Endian, Big Endian D Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) SPRS292B − OCTOBER 2005 − REVISED JUNE 2006 D 32-Bit External Memory Interface (EMIF) − Glueless Interface to Asynchronous Memories: SRAM and EPROM − Glueless Interface to Synchronous Memories: SDRAM and SBSRA...