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TMS320DM6467 Dataheets PDF



Part Number TMS320DM6467
Manufacturers Texas Instruments
Logo Texas Instruments
Description Digital Media System-on-Chip DMSoC
Datasheet TMS320DM6467 DatasheetTMS320DM6467 Datasheet (PDF)

TMS320DM6467 www.ti.com SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 TMS320DM6467 Digital Media System-on-Chip Check for Samples: TMS320DM6467 1 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture – 594-, 729-MHz C64x+™ Clock Rate – 32K-Byte L1P Program RAM/Cache (Direct – 297-, 364.5-MHz ARM926EJ-S™ Clock Rate Mapped) – Eight 32-Bit C64x+ Instructions/Cycle – 4752, 5832 C64x+ MIPS – Fully Software-Compatible With.

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TMS320DM6467 www.ti.com SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 TMS320DM6467 Digital Media System-on-Chip Check for Samples: TMS320DM6467 1 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture – 594-, 729-MHz C64x+™ Clock Rate – 32K-Byte L1P Program RAM/Cache (Direct – 297-, 364.5-MHz ARM926EJ-S™ Clock Rate Mapped) – Eight 32-Bit C64x+ Instructions/Cycle – 4752, 5832 C64x+ MIPS – Fully Software-Compatible With C64x/ARM9™ – Supports SmartReflex™ [-594 only] • Class 0 • 1.05-V and 1.2-V Adaptive Core Voltage – Extended Temp Available [-594 only] – Industrial Temp Available [-729 only] • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core – Eight Highly Independent Functional Units • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock – 32K-Byte L1D Data RAM/Cache (2-Way SetAssociative) – 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) • ARM926EJ-S Core – Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets – DSP Instruction Extensions and Single Cycle MAC – ARM® Jazelle® Technology – EmbeddedICE-RT™ Logic for Real-Time Debug • ARM9 Memory Architecture – 16K-Byte Instruction Cache – 8K-Byte Data Cache – 32K-Byte RAM – 8K-Byte ROM Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Embedded Trace Buffer™ (ETB11™) With 4KB Results) per Clock Cycle Memory for ARM9 Debug – Load-Store Architecture With Non-Aligned • Endianness: Little Endian for ARM and DSP Support • Dual Programmable High-Definition Video – 64 32-Bit General-Purpose Registers Image Co-Processor (HDVICP) Engines – Instruction Packing Reduces Code Size – Supports a Range of Encode, Decode, and – All Instructions Conditional Transcode Operations – Additional C64x+™ Enhancements • H.264, MPEG2, VC1, MPEG4 SP/ASP • Protected Mode Operation • 99-/108-MHz Video Port Interface (VPIF) • Exceptions Support for Error Detection and Program Redirection • Hardware Support for Modulo Loop Operation • C64x+ Instruction Set Features – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions – Additional Instructions to Support Complex Multiplies – Two 8-Bit SD (BT.656), Single 16-Bit HD (BT.1120), or Single Raw (8-/10-/12-Bit) Video Capture Channels – Two 8-Bit SD (BT.656) or Single 16-Bit HD (BT.1120) Video Display Channels • Video Data Conversion Engine (VDCE) – Horizontal and Vertical Downscaling – Chroma Conversion (4:2:2↔4:2:0) • Two Transport Stream Interface (TSIF) Modules (One Parallel/Serial and One Serial Only) – TSIF for MPEG Transport Stream – Simultaneous Synchronous or Asynchronous Input/Output Streams 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2012, Texas Instruments Incorporated TMS320DM6467 SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 – Absolute Time Stamp Detection – PID Filter With 7 PID Filter Tables – Corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery • External Memory Interfaces (EMIFs) – 297-/310.5-MHz 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O) – Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach • Flash Memory Interfaces – NOR (8-/16-Bit-Wide Data) – NAND (8-/16-Bit-Wide Data) • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) – Programmable Default Burst Size • 10/100/1000 Mb/s Ethernet MAC (EMAC) – IEEE 802.3 Compliant (3.3-V I/O Only) – Supports MII and GMII Media Independent Interfaces – Management Data I/O (MDIO) Module • USB Port With Integrated 2.0 PHY – USB 2.0 High-/Full-Speed Client – USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) • 32-Bit, 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface – Conforms to PCI Specification 2.3 • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) • One 64-Bit Watchdog Timer www.ti.com • Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals) – Supports up to 1.8432 Mbps UART – SIR and MIR (0.576 MBAUD) – CIR With.


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