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TMS320DM6467T Dataheets PDF



Part Number TMS320DM6467T
Manufacturers Texas Instruments
Logo Texas Instruments
Description Digital Media System-on-Chip DMSoC
Datasheet TMS320DM6467T DatasheetTMS320DM6467T Datasheet (PDF)

TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 TMS320DM6467T Digital Media System-on-Chip Check for Samples: TMS320DM6467T 1 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • High-Performance Digital Media SoC – 1-GHz C64x+™ Clock Rate – 500-MHz ARM926EJ-S™ Clock Rate – Eight 32-Bit C64x+ Instructions/Cycle – 8000 C64x+ MIPS – Fully Software-Compatible With C64x / ARM9™ – Industrial Temperature Devices Available • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+.

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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 TMS320DM6467T Digital Media System-on-Chip Check for Samples: TMS320DM6467T 1 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • High-Performance Digital Media SoC – 1-GHz C64x+™ Clock Rate – 500-MHz ARM926EJ-S™ Clock Rate – Eight 32-Bit C64x+ Instructions/Cycle – 8000 C64x+ MIPS – Fully Software-Compatible With C64x / ARM9™ – Industrial Temperature Devices Available • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core – Eight Highly Independent Functional Units • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle – 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) • ARM926EJ-S Core – Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets – DSP Instruction Extensions and Single Cycle MAC – ARM® Jazelle® Technology – EmbeddedICE-RT™ Logic for Real-Time Debug • ARM9 Memory Architecture – 16K-Byte Instruction Cache – 8K-Byte Data Cache – 32K-Byte RAM • Two Multipliers Support Four 16 x 16-Bit – 8K-Byte ROM Multiplies (32-Bit Results) per Clock • Embedded Trace Buffer™ (ETB11™) With 4KB Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Memory for ARM9 Debug Results) per Clock Cycle • Endianness: Little Endian for ARM and DSP – Load-Store Architecture With Non-Aligned Support • Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines – 64 32-Bit General-Purpose Registers – Supports a Range of Encode, Decode, and – Instruction Packing Reduces Code Size Transcode Operations – All Instructions Conditional • H.264, MPEG2, VC1, MPEG4 SP/ASP – Additional C64x+™ Enhancements • 150-MHz Video Port Interface (VPIF) • Protected Mode Operation – Two 8-Bit SD (BT.656), Single 16-Bit HD • Exceptions Support for Error Detection and Program Redirection (BT.1120), or Single Raw (8-/10-/12-Bit) Video Capture Channels • Hardware Support for Modulo Loop Operation – Two 8-Bit SD (BT.656) or Single 16-Bit HD (BT.1120) Video Display Channels • C64x+ Instruction Set Features • Video Data Conversion Engine (VDCE) – Byte-Addressable (8-/16-/32-/64-Bit Data) – Horizontal and Vertical Downscaling – 8-Bit Overflow Protection – Chroma Conversion (4:2:2↔4:2:0) – Bit-Field Extract, Set, Clear • Two Transport Stream Interface (TSIF) Modules – Normalization, Saturation, Bit-Counting (One Parallel/Serial and One Serial Only) – Compact 16-Bit Instructions – TSIF for MPEG Transport Stream – Additional Instructions to Support Complex Multiplies – Simultaneous Synchronous or Asynchronous Input/Output Streams • C64x+ L1/L2 Memory Architecture – Absolute Time Stamp Detection – 32K-Byte L1P Program RAM/Cache (Direct – PID Filter With 7 PID Filter Tables Mapped) – Corresponding Clock Reference Generator – 32K-Byte L1D Data RAM/Cache (2-Way SetAssociative) (CRGEN) Modules for System Time-Clock Recovery 1 Please be aware that an important notice concerning availability.


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