TMS320DM647

TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 TMS320DM647/TMS320DM648 Digital Media Processor Check for Samples: TMS320DM647, TMS320DM648 1 Features 1 High-Performance Digital Media Processor C64x+ L1/L2 Memory Architecture – 720-MHz, 800-MHz, 900-MHz, 1.1-GHz – 256K-bit (32K-byte) L1P Program RAM/Cache C64x+™ Clock Rates [Direct Mapped] – 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900), – 256K-bit (32K-byte) L1D Data RAM/Cache 0.91 ns (-1100) Instruction Cycle Time [2-Way Set-Associative] – 5760, 6400, 7200, 8800 MIPS – 2M-bit/256K-byte (DM647) or 4M-Bit/512K- – Eight 32-Bit C64x+ Instructions/Cycle – Fully Software-Compatible With C64x/Debug byte) (DM648) L2 Unified Mapped RAM/Cache [Flexible Allocation] – Commercial Temperature Ranges (-720, -900, and -1100 only) – Extended Temperature Ranges (-800 only) – Industrial Temperature Ranges (-720, -900, and -1100 only) VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core – Eight Highly Independent Functional Units With VelociTI.2 Extensions: Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16-bit Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit Results) per Clock Cycle Supports Little Endian Mode Only Five Configurable Video Ports – Providing a Glueless I/F to Common Video Decoder and Encoder De...