TMS320VC5506

TMS320VC5506 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS375C October 2006 − Revised January 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Revision History REVISION HISTORY This revision history highlights the technical changes made to SPRS375B to generate SPRS375C. PAGE(S) NO. 17 Table 2−3, Signal Descriptions: ADDITIONS/CHANGES/DELETIONS − Updated/changed GPIO.A[13:0] FUNCTION description from “... External Bus Selection Register is 11. ... enabling the Data EMIF mode.” to “... External Bus Selection Register is 00, enabling the Data EMIF mode.” 18 Table 2−3, Signal Descriptions (Continued): − Updated/changed A[15:14] RESET CONDITION description from “... GPIO0 = 0: Input, GPIO.A[15:14]” to “... GPIO0 = 0: Reserved” − Updated/changed D[15:0] FUNCTION description from “... The data bus keepers are disabled at reset, ...” to “... The data bus keepers are enabled at reset, ...”. 37 Figure 3−5, External Bus Selection Register: − Updated/changed reset value for Parallel Port Mode (EBSR.[1:0]) 61 Table 3−31, External Bus Selection Register: − Deleted “Hardware reset; x denotes a “don’t care.” footnote − Updated/changed the “The reset value is ...” footnote 62 Table 3−32, Interrupt Table: − Updated/changed the SOFTWARE (TRAP) EQUIVALENT “SINT10” to...