SN65LVDT33-EP

SN65LVDS33-EP, SN65LVDT33-EP www.ti.com SGLS309B – JUNE 2005 – REVISED APRIL 2007 HIGH-SPEED DIFFERENTIAL RECEIVER FEATURES Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of Up to –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) 400-Mbps Signaling Rate (2) and 200-Mxfr/s Data Transfer Rate Operates With a Single 3.3-V Supply –4 V to 5 V Common-Mode Input Voltage Range Differential Input Thresholds < ±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range Integrated 110-Ω Line Termination Resistors On LVDT Products Complies With TIA/EIA-644 (LVDS) Active Failsafe Assures a High-Level Output With No Input Bus-Pin ESD Protection Exceeds 15-kV HBM Input Remains High-Impedance On Power Down TTL Inputs Are 5-V Tolerant Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B DESCRIPTION This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option. Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowl...