CD54HCT20

CDx4HCT20 Dual 4-Input NAND Gates CD74HCT20, CD54HCT20 SCHS417 – JUNE 2020 1 Features 3 Description LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V CMOS input logic compatible – II ≤ 1 µA at VOL, VOH Buffered inputs 4.5 V to 5.5 V operation Wide operating temperature range: -55°C to +125°C Supports fanout up to 10 LSTTL loads Significant power reduction compared to LSTTL logic ICs 2 Applications This device contains two independent 4-input NAND gates. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT20M SOIC (14) 8.70 mm × 3.90 mm CD74HCT20E PDIP (14) 19.30 mm × 6.40 mm CD54HCT20F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Alarm / tamper detect circuit S-R latch 1 1A 2 1B 3 NC 4 1C 5 1D 6 1Y 7 GND 14 VCC 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y Functional pinout An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74HCT20, CD54HCT20 SCHS417 – JUNE 2020 www.ti.com Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description........................................