CD74HCT132

www.ti.com CD74HCT132, CD54HCT132 CD74HSCCTH1S33299, C– JDA5N4UHARCYT2103221 SCHS399 – JANUARY 2021 CDx4HCT132 Quadruple 2-Input NAND Gates with TTL-Compatible Schmitt-Trigger Inputs 1 Features LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V CMOS input logic compatible – II ≤ 1 µA at VOL, VOH Buffered inputs 4.5 V to 5.5 V operation Wide operating temperature range: –55°C to +125°C Supports fanout up to 10 LSTTL loads Significant power reduction compared to LSTTL logic ICs 2 Applications Alarm / tamper detect circuit S-R latch 3 Description This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B in positive logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HCT132M SOIC (14) 8.65 mm × 3.90 mm CD74HCT132E PDIP (14) 19.30 mm × 6.40 mm CD54HCT132J CDIP (14) 19.94 mm × 7.62 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y Device functional pinout CopyrighAtn©I2M0P21OTReTxaAsNInTsNtruOmTeInCtsEInactotrhpeoreatnedd of this data sheet addresses availability, warranty, changes, use iSnusbamfeittyD-corcituicmael anpt pFleiceadtbioancsk, 1 intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: CD74HCT132 CD54HCT132 CD74HCT132, CD54HCT132 SCHS399 – JANUARY 2021 www.ti...