SN74HC273-Q1

SN74HC273ĆQ1 OCTAL DĆTYPE FLIPĆFLOP WITH CLEAR SCLS578A − MARCH 2004 − REVISED APRIL 2008 D Qualified for Automotive Applications D Individual Data Input to Each Flip-Flop D Wide Operating Voltage Range of 2 V to 6 V D Applications Include: D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 160-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max − Buffer/Storage Registers − Shift Registers − Pattern Generators DW OR PW PACKAGE (TOP VIEW) D Contain Eight Flip-Flops With Single-Rail Outputs CLR 1 1Q 2 20 VCC 19 8Q D Direct Clear Input 1D 3 2D 4 18 8D 17 7D 2Q 5 16 7Q description/ordering information 3Q 6 3D 7 15 6Q 14 6D This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup 4D 8 4Q 9 GND 10 13 5D 12 5Q 11 CLK time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. ORDERING INFORMATION{ TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C SOIC − DW TSSOP − PW Reel of 2000 Reel of 2000 SN74HC273QDWRQ1 SN74HC273QPWRQ1 HC273Q HC273Q † For the most current package and ordering information, see the Package Option Addendum at the e...