SN74AUP1T86

SN74AUP1T86 ZZZWLFRPSCES805 – APRIL 2010±5(9,6('0$5&+ LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-OR GATE Check for Samples: SN74AUP1T86 FEATURES 1 Single-Supply Voltage Translator Output Level Up to Supply VCC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at VCC = 2.5 V) – 3.3 V to 2.5 V (at VCC = 2.5 V Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity Ioff Supports Partial Power Down (VCC = 0 V) Very Low Static Power Consumption: 0.1 µA Very Low Dynamic Power Consumption: 0.9 µA Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Pb-Free Packages Available: SC-70 (DCK) 2 x 2.1 x 0.65 mm (Height 1.1 mm) More Gate Options Available at www.ti.com/littlelogic ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) A 1 B 2 5 V CC GND 3 4 Y DESCRIPTION/ORDERING INFORMATION The SN74AUP1T86 performs the Boolean function Y = A Å B or Y = AB + AB with designation for logic-level translation applications with output referenced to supply VCC. AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept...