SN65EPT22

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN65EPT22 SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014 SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer 1 Features 1 Dual 3.3V LVTTL to LVPECL Buffer Operating Range – LVPECL VCC = 3.0 V to 3.6 V With GND = 0 V Support for Clock Frequencies to 2.0 GHz (typ) 420 ps Typical Propagation Delay Deterministic HIGH Output Value for Open Input Conditions Built-in Temperature Compensation Drop in Compatible to MC100ELT23 PNP Single Ended Inputs for Minimal Loading 3 Description The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level when inputs are in open condition. The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN65EPT22 SOIC (8) VSSOP (8) 4.90mm x 3.91mm 3.00mm x 3.00mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 2 Applications Data and Clock Transmission Over Backplane Signaling Level Conversion 4 Simplified Schematic Transmission Line ZO VTERM = VCC - 2 V Rt ~~ ZO SN65EPT22 LVPECL Transmission Line ZO Rt ~~ ZO VTERM = VCC - 2 V 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and othe...