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SN65EPT23 Dataheets PDF



Part Number SN65EPT23
Manufacturers Texas Instruments
Logo Texas Instruments
Description 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator
Datasheet SN65EPT23 DatasheetSN65EPT23 Datasheet (PDF)

SN65EPT23 www.ti.com SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator Check for Samples: SN65EPT23 FEATURES 1 • Dual 3.3 V Differential LVPECL/LVDS to LVTTL/LVCMOS Buffer Translator • 24 mA LVTTL Ouputs • Operating Range – VCC = 3.0 V to 3.6 V – GND = 0 V • Support for Clock Frequencies > 300 MHz • 2.0 ns Typical Propagation Delay • Built-in Temperature Compensation • Drop in Compatible to MC100EPT23 APPLICATIONS • Data and Clock Tra.

  SN65EPT23   SN65EPT23



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SN65EPT23 www.ti.com SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator Check for Samples: SN65EPT23 FEATURES 1 • Dual 3.3 V Differential LVPECL/LVDS to LVTTL/LVCMOS Buffer Translator • 24 mA LVTTL Ouputs • Operating Range – VCC = 3.0 V to 3.6 V – GND = 0 V • Support for Clock Frequencies > 300 MHz • 2.0 ns Typical Propagation Delay • Built-in Temperature Compensation • Drop in Compatible to MC100EPT23 APPLICATIONS • Data and Clock Transmission Over Backplane • Signaling Level Conversion for Clock or Data DESCRIPTION The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device. The device includes circuitry to maintain inputs at Vcc/2 when left open. The SN65EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option. spacer PINOUT ASSIGNMENT D0 1 D0 2 D1 3 D1 4 + + LVPECL + + + 8 VCC 7 Q0 LVTTL 6 Q1 5 GND Table 1. Pin Description PIN Q0, Q1 D0, D 0, D1, D 1 VCC GND FUNCTION LVTTL/LVCMOS Outputs Differential LVPECL/LVDS/CML Inputs Positive Supply Ground PART NUMBER SN65EPT23D/DR SN65EPT23DGK/DGKR ORDERING INFORMATION(1) PART MARKING PACKAGE EPT23 SOIC SSTI MSOP (1) Leaded device option not initially available; contact TI sales representative for further information. LEAD FINISH NiPdAu NiPdAu 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2009–2011, Texas Instruments Incorporated SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS PARAMETER CONDITION Absolute supply voltage, VCC Absolute input voltage, VI Output current GND = 0V GND = 0 and Vi ≤ VCC Continuous Surge Operating temperature range Storage temperature range VALUE 3.8 0 to 3.8 50 100 –40 to 85 –65 to 150 UNIT V V mA °C °C POWER DISSIPATION RATINGS PACKAGE CIRCUIT BOARD MODEL POWER RATING TA < 25°C (mW) SOIC Low-K 719 High-K 840 MSOP Low-K 469 High-K 527 THERMAL RESISTANCE, JUNCTION TO AMBIENT NO AIRFLOW 139 119 213 189 DERATING FACTOR TA > 25°C (mW/°C) 7 8 5 5 POWER RATING TA = 85°C (mW) 288 336 188 211 T.


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