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M95080-R Dataheets PDF



Part Number M95080-R
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description 8-Kbit serial SPI bus EEPROM
Datasheet M95080-R DatasheetM95080-R Datasheet (PDF)

SO8N (150 mil width) TSSOP8 (169 mil width) UFDFPN8 (MC) DFN8 (2 x 3 mm) Product status link M95080-DF M95080-R M95080-W Product label M95080-W M95080-R M95080-DF Datasheet 8-Kbit serial SPI bus EEPROM with high-speed clock Features SPI interface • Compatible with the serial peripheral interface (SPI) bus Memory • 8-Kbit (1 Kbyte) of EEPROM • Page size: 32 bytes Additional write lockable page (identification page) Supply voltage • Wide single supply voltage: – 2.5 V to 5.5 V for M95080-W – 1.8 .

  M95080-R   M95080-R


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SO8N (150 mil width) TSSOP8 (169 mil width) UFDFPN8 (MC) DFN8 (2 x 3 mm) Product status link M95080-DF M95080-R M95080-W Product label M95080-W M95080-R M95080-DF Datasheet 8-Kbit serial SPI bus EEPROM with high-speed clock Features SPI interface • Compatible with the serial peripheral interface (SPI) bus Memory • 8-Kbit (1 Kbyte) of EEPROM • Page size: 32 bytes Additional write lockable page (identification page) Supply voltage • Wide single supply voltage: – 2.5 V to 5.5 V for M95080-W – 1.8 V to 5.5 V for M95080-R – 1.7 V to 5.5 V for M95080-DF Temperature • Operating temperature range: from -40 °C up to +85 °C Fast write cycle time • Byte and page write within 5 ms High speed clock frequency • Clock up to 20 MHz Performance • Enhanced ESD protection • More than 4 million write cycles • More than 200-year data retention Advanced features • Write protect: quarter, half or whole memory array Package • RoHS-compliant and halogen-free (ECOPACK2): – SO8 – TSSOP8 – UFDFPN8 DS8776 - Rev 5 - September 2023 For further information contact your local STMicroelectronics sales office. www.st.com M95080-W M95080-R M95080-DF Description 1 Description The M95080 devices are electrically erasable programmable memories (EEPROMs) organized as 1024 x 8 bits, accessed through the SPI bus. The M95080-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95080-R can operate with a supply voltage from 1.8 V to 5.5 V and the M95080-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C. The M95080-D offers an additional page, named the Identification page (32 bytes). The Identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode. Figure 1. Logic diagram VCC D C S M95xxx Q W HOLD VSS The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when Chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low. C D Q S W HOLD VCC VSS Signal name Table 1. Signal names Serial clock Serial data input Serial data output Chip select Write protect Hold Supply voltage Ground Function Input Input Output Input Input Input - Direction DS8776 - Rev 5 page 2/45 M95080-W M95080-R M95080-DF Description Figure 2. 8-pin package connections (top view) M95xxx S1 Q2 W3 VSS 4 8 VCC 7 HOLD 6C 5D 1. See Section 10 Package information for package dimensions, and how to identify pin 1. DS8776 - Rev 5 page 3/45 M95080-W M95080-R M95080-DF Block diagram 2 Block diagram The memory is organized as shown in the following figure. Figure 3. Block diagram _ S Q _ W I/O D C ___ HOLD Data register + ECC Status register Control logic Sense amplifier Page latches Array Custom area* HV generator + Sequencer X decoder Address register Y decoder DT73076V1 *: Identification page. DS8776 - Rev 5 page 4/45 M95080-W M95080-R M95080-DF Signal description 3 Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in DC and AC parameters). These signals are described next. 3.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial clock (C). 3.2 Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial clock (C). 3.3 Serial clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial data input (D) are latched on the rising edge of Serial clock (C). Data on Serial data output (Q) change from the falling edge of Serial clock (C). 3.4 Chip select (S) When this input signal is high, the device is deselected and Serial data output (Q) is at high impedance. The device is in the Standby power mode, unless an internal Write cycle is in progress. Driving Chip select (S) low selects the device, placing it in the Active power mode. After power-up, a falling edge on Chip select (S) is required prior to the start of any instruction. 3.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial data output (Q) is high impedance, and Serial data input (D) and Serial clock (C) are Don’t care. To start the Hold condition, the device must be selected, with Chip select (S) driven low. 3.6 Write protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bit.


M95080-W M95080-R M95080-DF


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