Document
bq29440, bq2944L0 bq29441, bq29442, bq29443, bq29449, bq2944L9
www.ti.com
SLUSA15C – JUNE 2010 – REVISED NOVEMBER 2010
Voltage Protection for 2-Series, 3-Series, or 4-Series Cell Li-Ion Batteries
(Second-Level Protection)
Check for Samples: bq29440, bq2944L0, bq29441, bq29442, bq29443, bq29449, bq2944L9
FEATURES
1
• 2-Series, 3-Series, or 4-Series Cell Secondary Protection
• External Capacitor-Controlled Delay Timer
• Low Power Consumption ICC < 2 µA Typical [VCELL(ALL) < VPROTECT]
• High-Accuracy Overvoltage Protection: ±25 mV with TA = 0°C to 60°C
• Fixed Overvoltage Protection Thresholds: 4.30 V, 4.35 V, 4.40 V, 4.45 V, 4.50 V
• Small 8L QFN Package
APPLICATIONS
• Second-Level Protection in Li-Ion Battery Packs – Notebook Computers – Power Tools – Portable Equipment and Instrumentation
DESCRIPTION
The bq2944x is a secondary overvoltage protection IC for 2-series, 3-series, or 4-series cell Li-Ion battery packs that incorporates a high-accuracy precision overvoltage detection circuit.
FUNCTION
The voltage of each cell in a battery pack is compared to an internal reference voltage. If any cells reach an overvoltage condition, the bq2944x device starts a timer that provides a delay proportional to the capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from a low state to a high state. An optional latch configuration is available that holds the OUT pin in a high state indefinitely after an overvoltage condition has satisfied the specified delay timer period. The latch is released when the CD pin is shorted to GND.
T T
DRB Package (Top View)
VC1 1 VC2 2 VC3 3 GND 4
8 OUT 7 VDD 6 CD 5 VC4
P0012-02
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq29440, bq2944L0 bq29441, bq29442, bq29443, bq29449, bq2944L9
SLUSA15C – JUNE 2010 – REVISED NOVEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
TA
–40°C to
+110°C
PART NUMBER
BQ29440 BQ2944L0 BQ29441 BQ29442 BQ29443 BQ29449 BQ2944L9
OUT PIN LATCH OPTION
No Yes No No No No Yes
Table 1. ORDERING INFORMATION(1)
PACKAGE
PACKAGE DESIGNATOR
PACKAGE MARKING
OVP
QFN-8
DRB
440 44L0 441 442 443 449 44L9
4.35 V 4.35 V 4.40 V 4.45 V 4.50 V 4.30 V 4.30 V
ORDERING INFORMATION(2)
TAPE AND REEL TAPE AND REEL
(LARGE) (3)
(SMALL) (4)
BQ29440DRBR
BQ29440DRBT
BQ2944L0DRBR BQ2944L0DRBT
BQ29441DRBR
BQ29441DRBT
BQ29442DRBR
BQ29442DRBT
BQ29443DRBR
BQ29443DRBT
BQ29449DRBR
BQ29449DRBT
BQ2944L9DRBR BQ2944L9DRBT
(1) Example: bq2944L0DRBR is a device with the OUT latch option with a VOV threshold of 4.35 V. Contact Texas Instruments for other VOV threshold options.
(2) For the most current package and ordering information, see the Package Addendum at the end of this document, or the TI website at www.ti.com.
(3) Large tape and reel quantity is 3,000 units. (4) Small tape and reel quantity is 250 units.
THERMAL INFORMATION
THERMAL METRIC(1)
qJA qJC(top) qJB yJT yJB qJC(bottom)
Junction-to-ambient thermal resistance(2) Junction-to-case(top) thermal resistance(3) Junction-to-board thermal resistance(4) Junction-to-top characterization parameter(5) Junction-to-board characterization parameter(6) Junction-to-case(bottom) thermal resistance(7)
bq2944x DRB
8 PINS 50.5 25.1 19.3 0.7 18.9 5.2
UNITS °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction tempera.