SN74ABT821A

D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs description SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 SN54ABT821 . . . JT OR W PACKAGE SN74ABT821A . . . DB, DW, OR NT PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 9D 10 10D 11 GND 12 24 VCC 23 1Q 22 2Q 21 3Q 20 4Q 19 5Q 18 6Q 17 7Q 16 8Q 15 9Q 14 10Q 13 CLK SN54ABT821 . . . FK PACKAGE (TOP VIEW) 2Q 1Q VCC NC OE 1D 2D These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the devices provide true data at the Q outputs. 4 3 2 1 28 27 26 3D 5 25 3Q 4D 6 24 4Q 5D 7 23 5Q NC 8 22 NC ...