SN74ABT827

SN54ABT827, SN74ABT827 10ĆBIT BUFFERS/DRIVERS WITH 3ĆSTATE OUTPUTS SCBS159E − JANUARY 1991 − REVISED APRIL 2005 D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation D Flow-Through Architecture Optimizes PCB Layout D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D High-Drive Outputs (−32-mA IOH, 64-mA IOL) D Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs description SN54ABT827 . . . JT PACKAGE SN74ABT827 . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) OE1 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 A9 10 A10 11 GND 12 24 VCC 23 Y1 22 Y2 21 Y3 20 Y4 19 Y5 18 Y6 17 Y7 16 Y8 15 Y9 14 Y10 13 OE2 SN54ABT827 . . . FK PACKAGE (TOP VIEW) A2 A1 OE1 NC VCC Y1 Y2 These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The ’ABT827 provides true data at the outputs. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be t...