SN54ABT162827A

D Members of the Texas Instruments Widebus  Family D Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required D High-Impedance State During Power Up and Power Down D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C D Distributed VCC and GND Pins Minimize High-Speed Switching Noise D Ioff and Power-Up 3-State Support Hot Insertion D Flow-Through Architecture Optimizes PCB Layout D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) description/ordering information The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1 and 1OE2, or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. SN54ABT162827A, SN74ABT162827A 20ĆBIT BUFFERS/DRIVERS WITH 3ĆSTATE OUTPUTS SCBS248F − JULY 1993 − REVISED JUNE 2004 SN54ABT162827A . . . WD PACKAGE SN74ABT162827A . . . DGG OR DL PACKAGE (TOP VIEW) 1OE1 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 1Y5 8 1Y6 9 1Y7 10 GND 11 1Y8 12 1Y9 13 1Y10 14 2Y1 15 2Y2 16 2Y3 17 GND 18 2Y4 19 2Y5 20 2Y6 21 VCC 22 2Y7...