SN54ABT16825

D Members of Texas Instruments’ Widebus™ Family D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17 D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D Distributed VCC and GND Pins Minimize High-Speed Switching Noise D Flow-Through Architecture Optimizes PCB Layout D High-Drive Outputs (–32-mA IOH, 64-mA IOL) description The ’ABT16825 devices are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as two 9-bit buffers or one 18-bit buffer. They provide true data. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all nine affected outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN54ABT16825, SN74ABT16825 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS218D – JUNE 1992 – REVISED OCTOBER 2000 SN54ABT16825 . . . WD PACKAGE SN74ABT16825 . . . DL PACKAGE (TOP VIEW) 1OE1 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 1Y5 8 1Y6 9 1Y7 10 GND 11 1Y8 12 1Y9 13 GND 14 G...