SN54ABT16833

SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D Flow-Through Architecture Optimizes PCB Layout D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Parity-Error Flag With Parity Generator/Checker D Register for Storage of Parity-Error Flag D Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings description The ’ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected. SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 SN54ABT16833 . . . WD PACKAGE SN74ABT16833 . . . DGG OR DL PACKAGE (TOP VIEW) 1OEB 1 1CLK 2 1ERR 3 GND 4 1A1 5 1A2 6 VCC 7 1A3...