20-BIT BUS-INTERFACE D-TYPE LATCHES
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED ...
Description
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
D Members of the Texas Instruments
Widebus ™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
description
These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
SN54ABT16841 . . . WD PACKAGE SN74ABT16841 . . . DL PACKAGE
(TOP VIEW)
1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 1Q7 10 GND 11 1Q8 12 1Q9 13 1Q10 14 2Q1 15 2Q2 16 2Q3 17 GND 18 2Q4 19 2Q5 20 2Q6 21 VCC 22 2Q7 23 2Q8 24 GND 25 2Q9 26 2Q10 27 2OE 28
56 1LE 55 1D1 54 1D2 53 GND 52 1D3 51 1D4 50 VCC 49 1D5 4...
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