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SN54ABT18504 Dataheets PDF



Part Number SN54ABT18504
Manufacturers Texas Instruments
Logo Texas Instruments
Description SCAN TEST DEVICE
Datasheet SN54ABT18504 DatasheetSN54ABT18504 Datasheet (PDF)

• Members of the Texas Instruments SCOPE ™ Family of Testability Products • Members of the Texas Instruments Widebus ™ Family • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture • UBT ™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode • Two Boundary-Scan Cells per I/O for Greater Flexibility • State-of-the-Art EPIC-ΙΙB ™ BiCMOS Design Significantly Reduces Power Diss.

  SN54ABT18504   SN54ABT18504


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• Members of the Texas Instruments SCOPE ™ Family of Testability Products • Members of the Texas Instruments Widebus ™ Family • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture • UBT ™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode • Two Boundary-Scan Cells per I/O for Greater Flexibility • State-of-the-Art EPIC-ΙΙB ™ BiCMOS Design Significantly Reduces Power Dissipation SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS108B – AUGUST 1992 – REVISED JUNE 1993 • SCOPE ™ Instruction Set – IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ – Parallel Signature Analysis at Inputs With Masking Option – Pseudo-Random Pattern Generation From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes • Packaged in 64-Pin Plastic Thin Quad Flat Pack Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat Pack Using 25-mil Center-to-Center Spacings SN54ABT18504 . . . HV PACKAGE (TOP VIEW) A3 A2 A1 GND OEBA LEBA TDO VCC NC TMS CLKBA CLKENBA B1 GND B2 B3 B4 A4 A5 A6 GND A7 A8 A9 A10 NC VCC A11 A12 A13 GND A14 A15 A16 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 B5 B6 B7 GND B8 B9 B10 VCC NC B11 B12 B13 B14 GND B15 B16 B17 A17 A18 A19 GND A20 CLKENAB CLKAB TDI NC VCC TCK LEAB OEAB GND B20 B19 B18 NC – No internal connection SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 1 SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS108B – AUGUST 1992 – REVISED JUNE 1993 SN74ABT18504 . . . PM PACKAGE (TOP VIEW) A3 A2 A1 GND OEBA LEBA TDO V CC TMS CLKBA CLKENBA B1 GND B2 B3 B4 A4 A5 A6 GND A7 A8 A9 A10 VCC A11 A12 A13 GND A14 A15 A16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 B5 B6 B7 GND B8 B9 B10 VCC B11 B12 B13 B14 GND B15 B16 B17 A17 A18 A19 GND A20 CLKENAB CLKAB TDI VCC TCK LEAB OEAB GND B20 B19 B18 description The SN54ABT18504 and SN74ABT18504 scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPE ™ testability IC family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE™ universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE ™ universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS108B – AUGUST 1992 – REVISED JUNE 1993 description (continued) Four dedicated test pins .


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