OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54ABT273, SN74ABT273
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997...
Description
SN54ABT273, SN74ABT273
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
SN54ABT273 . . . J OR W PACKAGE SN74ABT273 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
CLR 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9
GND 10
20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK
description
The ’ABT273 are 8-bit positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D input signal has no effect at the output.
4Q GND CLK
5Q 5D
SN54ABT273 . . . FK PACKAGE (TOP VIEW)
1D 1Q CLR VCC ...
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