SN54ABT2827

D Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Flow-Through Architecture Optimizes PCB Layout D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs SN54ABT2827, SN74ABT2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS648A – DECEMBER 1995 – REVISED JANUARY 1997 SN54ABT2827 . . . JT PACKAGE SN74ABT2827 . . . DW OR NT PACKAGE (TOP VIEW) OE1 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 A9 10 A10 11 GND 12 24 VCC 23 Y1 22 Y2 21 Y3 20 Y4 19 Y5 18 Y6 17 Y7 16 Y8 15 Y9 14 Y10 13 OE2 description These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The ’ABT2827 provide true data at their outputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. A9 A10 GND NC OE2 Y10 Y9 SN54ABT2827 . . . FK PACKAGE (TOP VIEW) A2 A1 OE1 NC VCC Y1 Y2 4 3 2 1...