SN54ABT2952A

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions D Noninverting Outputs D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D Latch-Up Performance Exceeds 500 mA Per JESD 17 D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs SN54ABT2952A . . . JT OR W PACKAGE SN74ABT2952A . . . DB, DW, PW, OR NT PACKAGE (TOP VIEW) B8 1 B7 2 B6 3 B5 4 B4 5 B3 6 B2 7 B1 8 OEAB 9 CLKAB 10 CLKENAB 11 GND 12 24 VCC 23 A8 22 A7 21 A6 20 A5 19 A4 18 A3 17 A2 16 A1 15 OEBA 14 CLKBA 13 CLKENBA SN54ABT2952A . . . FK PACKAGE (TOP VIEW) A7 A8 VCC NC B8 B7 B6 description The ’ABT2952A transceivers consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on e...