SN74ABT646

State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (– 32-mA IOH, 64-mA IOL ) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs description SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E – JULY 1991 – REVISED JULY 1994 SN54ABT646 . . . JT PACKAGE SN74ABT646 . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) CLKAB 1 SAB 2 DIR 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 A8 11 GND 12 24 VCC 23 CLKBA 22 SBA 21 OE 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 B8 SN54ABT646 . . . FK PACKAGE (TOP VIEW) DIR SAB CLKAB NC VCC CLKBA SBA These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′ABT646. Output-enable (OE) and direction-control (DIR) input...