Document
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs
description
SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
SN54ABT652A . . . JT OR W PACKAGE SN74ABT652A . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
CLKAB 1 SAB 2
OEAB 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 A8 11
GND 12
24 VCC 23 CLKBA 22 SBA 21 OEBA 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 B8
SN54ABT652A . . . FK PACKAGE (TOP VIEW)
OEAB SAB CLKAB NC VCC CLKBA SBA
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select either real-time or stored data for transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’ABT652A.
4 3 2 1 28 27 26
A1 5
25 OEBA
A2 6
24 B1
A2 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6 11
19 B5
12 13 14 15 16 17 18
A7 A8 GND NC B8 B7 B6
NC – No internal connection
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control inputs. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
SN54ABT652A, SN74ABT652A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS072F – JANUARY 1991 – REVISED MAY 1997
description (continued)
The SN54ABT652A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT652A is characterized for operation from –40°C to 85°C.
INPUTS OEAB OEBA CLKAB CLKBA
SAB
FUNCTION TABLE DATA I/O†
SBA
A1–A8
B1–B8
OPERATION OR FUNCTION
L
H
H or L H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
Input
X
H
↑
H or L
X
X
Input
Unspecified‡
H
H
↑
↑
X‡
X
Input
Output
L
X
H or L
↑
X
X
Unspecified‡
Input
L
L
↑
↑
X
X‡
Output
Input
Store A and B data Store A, hold B
Store A in both registers Hold A, store B
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L H or L
H
H
Output
Output
Stored A data to B bus and stored B data to A bus
† The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occ.