Document
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
D Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are Required
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D Typical VOLV (Output Undershoot) < 0.5 V at
VCC = 5 V, TA = 25°C
D Package Options Include Plastic
Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and DIPs (JT)
description
These 12-bit buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
SN54ABT5403 . . . JT PACKAGE SN74ABT5403 . . . DW PACKAGE
(TOP VIEW)
Y1 1 Y2 2 Y3 3 Y4 4 Y5 5 Y6 6 GND 7 Y7 8 Y8 9 Y9 10 Y10 11 Y11 12 Y12 13 OE1 14
28 D1 27 D2 26 D3 25 D4 24 D5 23 D6 22 D7 21 VCC 20 D8 19 D9 18 D10 17 D11 16 D12 15 OE2
SN54ABT5403 . . . FK PACKAGE (TOP VIEW)
D9
D8
VCC
D7
D6
D5
D4
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all 12 outputs are in the high-impedance state. These devices provide inverted data.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Y5
Y6
GND
Y7
4 3 2 1 28 27 26
D3 5
25 D10
D2 6
24 D11
D1 7
23 D12
Y1 8
22 OE2
Y2 9
21 OE1
Y3 10
20 Y12
Y4 11
19 Y11
12 13 14 15 16 17 18
Y8
Y9
Y10
The SN54ABT5403 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT5403 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS OE1 OE2 D
OUTPUT Y
L
L
L
H
L
L
H
L
H
X
X
Z
X
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1997, Texas Instruments Incorporated 1
SN54ABT5403, SN74ABT5403 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
logic symbol†
14 OE1
15 OE2
& EN
logic diagram (positive logic)
OE1 14 OE2 15
28
28
1
D1
1 Y1
D1
1
Y1
27
2
D2
Y2
26
3
D3 25
Y3 4
To 11 Other Channels
D4
Y4
24
5
D5
Y5
23
6
D6
Y6
22
8
D7
Y7
20
9
D8
Y8
19
10
D9
Y9
18
11
D10
Y10
17
12
D11
Y11
16
13
D12
Y12
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW and JT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-r.