SN74ABT125Q-Q1

D Qualified for Automotive Applications D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C D High-Drive Outputs (−16-mA IOH, 32-mA IOL) D Ioff and Power-Up 3-State Support Hot Insertion D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN74ABT125Q-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS686B − DECEMBER 2002 − REVISED JANUARY 2008 D PACKAGE (TOP VIEW) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y description/ordering information The SN74ABT125Q-Q1 quadruple bus buffer gate features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION† TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C SOIC − D Tape and reel SN74ABT125QDRQ...