Document
D Typical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up
and Power Down
D High-Drive Outputs (−32-mA IOH, 64-mA IOL)
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS183H − FEBRUARY 1991 − REVISED MAY 2003
D Ioff and Power-Up 3-State Support Hot
Insertion
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A)
SN54ABT126 . . . J PACKAGE SN74ABT126 . . . D, DB, N, NS,
OR PW PACKAGE (TOP VIEW)
1OE 1 1A 2 1Y 3
2OE 4 2A 5 2Y 6
GND 7
14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y
SN74ABT126 . . . RGY PACKAGE (TOP VIEW)
1OE VCC
1 1A 2 1Y 3 2OE 4 2A 5 2Y 6
7
14 13 4OE 12 4A 11 4Y 10 3OE 9 3A
8
SN54ABT126 . . . FK PACKAGE (TOP VIEW)
1A 1OE NC VCC 4OE
1Y NC 2OE NC 2A
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A NC 4Y NC 3OE
2Y GND
NC 3Y 3A
GND 3Y
description/ordering information
NC − No internal connection
The ’ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE PART NUMBER
TOP-SIDE MARKING
QFN − RGY
Tape and reel SN74ABT126RGYR
AB126
−40°C to 85°C
PDIP − N
SOIC − D SOP − NS SSOP − DB
Tube Tube Tape and reel Tape and reel Tape and reel
SN74ABT126N SN74ABT126D SN74ABT126DR SN74ABT126NSR SN74ABT126DBR
SN74ABT126N
ABT126 ABT126 AB126
TSSOP − PW
Tube Tape and reel
SN74ABT126PW SN74ABT126PWR
AB126
CDIP − J −55°C to 125°C
LCCC − FK
Tube Tube
SNJ54ABT126J SNJ54ABT126FK
SNJ54ABT126J SNJ54ABT126FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2003, Texas Instruments Incorporated 1
SN54ABT126, SN74ABT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS183H − FEBRUARY 1991 − REVISED MAY 2003
FUNCTION TABLE (each buffer)
INPUTS
OE
A
OUTPUT Y
H
H
H
H
L
L
L
X
Z
logic diagram (positive logic)
1OE 1 2
1A
3 1Y
3OE 10 9
3A
8 3Y
2OE 4 5
2A
6 2Y
4OE 13 12
4A
11 4Y
Pin numbers shown are for the D, DB, J, N, NS, PW, and RGY packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°.