18-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JUL...
Description
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
D Members of the Texas Instruments
Widebus ™ Family
D B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors Are Required
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D UBT ™ (Universal Bus Transceiver)
Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up
and Power Down
D Flow-Through Architecture Optimizes PCB
Layout
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
description
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs.
SN54ABT162601 . . . WD PACKAGE SN74ABT162601 . . . DGG OR DL PACKAGE
(TOP VIEW)
OEAB 1 LEAB 2
A1 3 GND 4
A2 5 A3 6 VCC 7 A4 8 A5 9 A6 10 GND 11 A7 12 A8 13 A9 14 A10 15 A11 16 A12 17 GN...
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