SN74ABTH18504A

SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS165C – AUGUST 1993 – REVISED JULY 1996 D Members of the Texas Instruments SCOPE™ Family of Testability Products D Members of the Texas Instruments Widebus™ Family D Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture D UBT ™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode D Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors D B-Port Outputs of ’ABTH182504A Devices Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required D State-of-the-Art EPIC-ΙΙB ™ BiCMOS Design D One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency D SCOPE ™ Instruction Set – IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ – Parallel-Signature Analysis at Inputs – Pseudo-Random Pattern Generation From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes D Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings SN54ABTH18504A, SN54ABTH182504A . . . HV PACKAGE (TOP VIEW) A3 A2 A1 GND OEBA LEBA TDO VCC NC TMS CLKBA CLKENBA B1 GND B2 B3 B4 A4 A5 A6 GND A7 A8 A9 A10 NC VCC A11 A12 A13 GND A14...