SN54ABTH32543

D Members of the Texas Instruments Widebus+™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D Released as DSCC SMD 5962-9557801NXD SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Package Options Include 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch and Space-Saving 100-Pin Ceramic Quad Flat (HS) Package† ’ABTH32543 . . . PZ PACKAGE (TOP VIEW) 1A8 1A7 1A6 GND 1A5 1A4 1A3 1A2 1A1 1CEBA 1OEBA 1LEBA VCC 1LEAB 1OEAB 1CEAB 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1A9 1A10 GND 1A11 1A12 1A13 1A14 GND 1A15 1A16 1A17 1A18 VCC 2A1 2A2 2A3 2A4 GND 2A5 2A6 2A7 2A8 GND 2A9 2A10 10099 98 9796 959493 92 91 90 89 88 87 86 85 84 83 8281 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 272829 3031 32 33 34 35 36 3738 3940 4142 43 44 45 46 474849 50 1B9 1B10 GND 1B11 1B12 1B13 1B14...