Document
AD120 Preliminary
Document Title 3-Level / 258 Outputs TFT LCD Gate Driver Revision History
Rev. No.
0.0
3-Level / 258 Outputs TFT LCD Gate Driver
History
Initial issue
Issue Date
August 10, 2001
Remark
Preliminary
Important Notice: AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC products in such applications is understood to be fully at the risk of the customer.
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology, Inc.
AD120 Preliminary
Features
n n n n n TFT LCD gate driver 3-level / 258 outputs 40V max. for each output -15V min. for each output 2.7V~3.6V logic input/output level n Bi-directional data shift control n Output waveform control n TCP available
3-Level / 258 Outputs TFT LCD Gate Driver
AD120 is a gate driver for TFT LCD panel. There are 258 outputs in the chip. Three-level output allows voltage correction for better switching noise rejection. It can be used for XGA / SXGA panels.
Block Diagram
ST1 ST2
ST1X
Shift Register
R/L CP
ST2X
.........
XOFF XON OGW
Decoder
.........
VH VOFF VL VDD VSS
Output
.........
OUT0 OUT1 OUT2
.........
OUT255 OUT256 OUT257
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AD120
TCP Pinout
18 19 20 21 22
OUT0 OUT1 OUT2 OUT3 OUT4
VL VOFF VH ST1 ST2 VSS CP VDD XOFF XON R/L OGW ST2X ST1X VH VOFF VL
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AD120
271 272 273 274 275
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OUT253 OUT254 OUT255 OUT256 OUT257
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AD120
Input/Output Pin Function
Pin No. 11 7 Symbol CP I/O I I Description Clock pulse Right / left direction control for shift register When R /L is LOW, data are shifted to the right, or ST1 / ST2 .… output257.
R /L
output0
output1
When R /L is HIGH, data are shifted to the left, or ST1X / ST2X output256 .... output0.
8
output257
XON XOFF
OGW ST1, ST2, ST1X, ST2X
I
XON to force all the outputs to VH voltage. It is not synchronous to CP. XOFF to force all the outputs to VOFF voltage.
It is not synchronous to CP. Output Gate pulse Width to select output_waveform format. When R /L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined as outputs . The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses. When R /L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined as outputs. The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses. Output drivers These outputs are synchronized to CP pulses. The output format and voltage level are controlled by OGW, XON , XOFF , ST1 / ST2, ST1X / ST2X and R /L correspondingly as shown in the diagram. Reference voltage Supply voltage for logic operation VDD and VSS are voltage levels of input / output logic signals High voltage for output drivers Low voltage for output drivers OFF voltage for output drivers
9
I
6 4,5, 13,14
I I/O
18 - 275
OUT0~ OUT257
O
12 10 3, 15 1, 17 2, 16
VSS VDD VH VL VOFF
PWR PWR PWR PWR PWR
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Description
Operation Output signals OUT0~OUT257 are used for control of the TFT gates of the LCD panel. A bi-directional shift register is implemented to sequentially output signals OUT0~OUT257. A clock pulse CP is applied to the bi-directional shift register and the direction of the register is controlled by R /L signal. When R /L is LOW and either starting signal ST1 or ST2 goes to HIGH, the shift register starts shifting from OUT0 to OUT257. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1X / ST2X switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. When R /L is HIGH and either starting signal ST1X or ST2X goes to HIGH, the shift register starts shifting from OUT257 to OUT0. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1/ST2 switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. 3-Level Output VH - VL = 40V(max.) VOFF - VL = 0~10V VH - VSS = 17~28V OUT VH
Level VDD VSS
VOFF VL
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Operation Diagram 1 ( R /L = L, OGW = L)
1 CP VDD ST1 V SS VDD ST2 V SS VH OUT0 VOFF VL VH OUT1 VOFF VL VH VOFF VL VH OUT3 VOFF VL VH OUT256 VOFF VL VH OUT257 VOF.