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PLA133-67 Data Sheet

Low-Power DC to 160MHz 1:6 Fanout Buffer

Download PLA133-67 Datasheet

PLA133-67
PLA133-67 Low-Power DC to 160 MHz 1:6 Fanout Buffer IC for Automotive Features • Automotive AEC-Q100 Qualified • 1:6 LVCMOS Output Fanout Buffer from DC to 160 MHz • Low Additive Phase Jitter of 60 fs RMS • 8 mA Output Drive Strength • Low Power Consumption for Portable Applications • Automotive Applications Grade 1 Compliant • Low Input-Output Delay • Output-Output Skew <250 ps • 2.5V to 3.3V, +10% Operation • 1.8V +10%/–5% Operation up to 67 MHz • Wide Temperature Range: –40°C to +125°C • Available in 16-Pin TSSOP Package Applications • Automotive Applications: - ADAS Vision System - Infotainment and Dashboard General Description The PLA133-67 is an advanced fanout buffer designed for automotive applications and other high performance, low-power, small form factor applications. The PLA133-67 accepts a reference clock input from DC to 160 MHz and provides six outputs of the same frequency with ultra-low additive jitter. The device is AEC-Q100 qualified. The PLA133-67 is available in.
PLA133-67

Download PLA133-67 Datasheet
PLA133-67 Low-Power DC to 160 MHz 1:6 Fanout Buffer IC for Automotive Features • Automotive AEC-Q100 Qualified • 1:6 LVCMOS Output Fanout Buffer from DC to 160 MHz • Low Additive Phase Jitter of 60 fs RMS • 8 mA Output Drive Strength • Low Power Consumption for Portable Applications • Automotive Applications Grade 1 Compliant • Low Input-Output Delay • Output-Output Skew <250 ps • 2.5V to 3.3V, +10% Operation • 1.8V +10%/–5% Operation up to 67 MHz • Wide Temperature Range: –40°C to +125°C • Available in 16-Pin TSSOP Package Applications • Automotive Applications: - ADAS Vision System - Infotainment and Dashboard General Description The PLA133-67 is an advanced fanout buffer designed for automotive applications and other high performance, low-power, small form factor applications. The PLA133-67 accepts a reference clock input from DC to 160 MHz and provides six outputs of the same frequency with ultra-low additive jitter. The device is AEC-Q100 qualified. The PLA133-67 is available in a TSSOP-16L package. The PLA133-67 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled. Functional Block Diagram  2020 Microchip Technology Inc. DS20006358C-page 1 PLA133-67 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Supply Voltage to Ground P.


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