Document
September 1996, ver. 1
®
a8255
Programmable Peripheral Interface Adapter
Features
General Description
s a8255 MegaCore function implementing a programmable peripheral interface adapter
s Optimized for FLEX® and MAX® architectures s 24 programmable inputs/outputs s Static read/write or handshaking modes s Direct bit set/reset capability s Synchronous design s Uses approximately 194 FLEX logic elements (LEs) s Functionally based on the Intel 8255A and Harris 82C55A devices,
except as noted in the “Variations & Clarifications” section on page 56
The a8255 MegaCore function implements a programmable peripheral interface adapter (see Figure 1). The a8255 has 24 I/O signals that can be programmed in two groups of 12. This MegaCore function operates in the following three modes:
s Mode 0: Basic Input/Output—Port A, port B, and port C (upper and lower) can be independently configured as inputs or outputs to read or hold static data. Outputs are registered; inputs are not registered.
s Mode 1: Strobed Input/Output—Port A and port B can be independently configured as strobed input or output buses. Signals from port C are dedicated as control signals for data handshaking.
s Mode 2: Bidirectional Bus—Port A can be configured as a bidirectional bus with the majority of port C providing the control signals. In this configuration, port B can still implement mode 0 or mode 1.
Figure 1. a8255 Symbol
A8255
CLK nCS nRD nWR RESET A[1..0] DIN[7..0] PAin[7..0] PBin[7..0] PCin[7..0]
PAEN PBEN DOUT[7..0] PAOUT[7..0] PBOUT[7..0] PCEN[7..0] PCOUT[7..0]
Altera Corporation
A-DS-A8255-01
45
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table 1 describes the input and output ports of the a8255.
Table 1. a8255 Ports
Name
clk ncs
Type
Input Input
nrd Input
nwr Input
reset
Input
a[1..0] din[7..0]
Input Input
pain[7..0] pbin[7..0] pcin[7..0] paen pben dout[7..0]
Input Input Input Output Output Output
paout[7..0] pbout[7..0] pcen[7..0]
Output Output Output
pcout[7..0] Output
Polarity
Description
– Low
Low
Low
High
High High
High High High High High High
High High High
High
Clock. Chip select. When ncs is asserted, the a8255 is selected and read and write transactions to internal registers are possible. Read control. When nrd is asserted and the a8255 is selected, read transactions from internal registers are possible. Write control. When nwr is asserted and the a8255 is selected, write transactions to internal registers are possible. Reset. Initializes the control and port C output registers, and sets the port A, B, and C registers to input mode. Register address bus. This bus selects one of the internal registers. Data input bus. The CPU writes data to the internal control, port A, port B, or port C register via the din[7..0] bus. Port A input data bus. Port B input data bus. Port C input data bus. Port A data enable. Output enable for the port A output data bus. Port B data enable. Output enable for the port B output data bus. Data output bus. The CPU reads data from the internal control, port A, port B, or port C register via the dout[7..0] bus. Port A output data bus. Port B output data bus. Port C data enable bus. Output enable for each bit of the port C output data bus. Port C output data bus.
46 Altera Corporation
Functional Description
a8255 Programmable Peripheral Interface Adapter Data Sheet
Figure 2 shows a block diagram of the a8255.
Figure 2. a8255 Block Diagram
reset ncs nrd nwr
a[1..0] din[7..0]
Control Register & Logic
Port Control Bus
dout[7..0]
Data Output Select
Data Output Multiplexer
Control Register Data
Port A Output Register
paen pben pcen[7..0]
paout[7..0]
Port A Input Register
pain[7..0]
Port B Output Register
pbout[7..0]
Port B Input Register
pbin[7..0]
Port C Status
Port C Output Register
& Control
pcout[7..0] pcin[7..0]
Altera Corporation
47
a8255 Programmable Peripheral Interface Adapter Data Sheet
Register Address Map
Table 2 shows the register address map for the a8255.
Table 2. Register Address Map
a1 a0
Register
0 0 Port A data (all modes) 0 1 Port B data (all modes) 1 0 Port C data (mode 0) and status (modes 1 and 2) 1 1 Control register mode definition and port C bit set/reset
Registers
This section describes the following a8255 registers:
s Control s Port A, B & C
Control Register
The control register sets the mode and signal direction for the three 8-bit I/O ports. Control of the I/O ports is split into two groups. Group A consists of port A and the upper four bits of port C; group B consists of port B and the lower four bits of port C. Group A can be set to mode 0, mode 1, or mode 2, but group B can be set to only mode 0 or mode 1.
Writing to the control register address with bit 7 set is the mode definition format, which allows control of the mode and direction of the three I/O ports (see Table 3). Writing to the control register address with bit 7 reset is the port C bit set/reset format, which allows single-bit co.