9639 Datasheet: N-CHANNEL 150V - 0.045 OHM - 5A SO-8 LOW GATE CHARGE STripFET POWER MOSFET





9639 N-CHANNEL 150V - 0.045 OHM - 5A SO-8 LOW GATE CHARGE STripFET POWER MOSFET Datasheet

Part Number 9639
Description N-CHANNEL 150V - 0.045 OHM - 5A SO-8 LOW GATE CHARGE STripFET POWER MOSFET
Manufacture STMicroelectronics
Total Page 16 Pages
PDF Download Download 9639 Datasheet PDF

Features: ST95P04 SERIAL ACCESS SPI BUS 4K (512 x 8) EEPROM NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETEN TION SINGLE 3V to 5.5V SUPPLY VOLTAGE S PI BUS COMPATIBLE SERIAL INTERFACE 1 MH z CLOCK RATE MAX BLOCK WRITE PROTECTION STATUS REGISTER 16 BYTE PAGE MODE WRIT E PROTECT SELF-TIMED PROGRAMMING CYCLE E.S.D.PROTECTION GREATER than 4000V The ST95P04 will be replaced shortly by th e updated version ST95040 8 1 PSDIP8 ( B) 0.25mm Frame 8 1 SO8 (M) Figure 1. Logic Diagram DESCRIPTION The ST95P04 is a 4K bit Electrically Erasable Progr ammable Memory (EEPROM) fabricated with SGS-THOMSON’s High Endurance Single Polysilicon CMOS technology. The 4K bit memory is organised as 32 pages of 16 bytes. The memory is accessed by a simp le SPI bus compatible serial interface. The bus signals are a serial clock inp ut (C), a serial data input (D) and a s erial data output (Q). The device conne cted to the bus is selected when the ch ip select input (S) goes low. Communications with the chip can be.

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ST95P04
SERIAL ACCESS SPI BUS 4K (512 x 8) EEPROM
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE 3V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
1 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
The ST95P04 will be replaced shortly by the
updated version ST95040
NOT FOR NEW DESIGN
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
DESCRIPTION
The ST95P04 is a 4K bit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
SGS-THOMSON’s High Endurance Single Polysili-
con CMOS technology. The 4K bit memory is or-
ganised as 32 pages of 16 bytes. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q). The device connected to the bus is selected
when the chip select input (S) goes low. Commu-
nications with the chip can be interrupted with a
hold input (HOLD). The write operation is disabled
by a write protect input (W).
Table 1. Signal Names
C
D
Q
S
W
HOLD
VCC
VSS
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
Figure 1. Logic Diagram
VCC
D
C
S
W
HOLD
ST95P04
VSS
Q
AI01063B
June 1996
1/16

                    
                    






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