96L02 Datasheet | Dual Retriggerable Resettable Monostable Multivibrator





(Datasheet) 96L02 Datasheet PDF Download

Part Number 96L02
Description Dual Retriggerable Resettable Monostable Multivibrator
Manufacture National Semiconductor
Total Page 6 Pages
PDF Download Download 96L02 Datasheet PDF

Features: 96L02 DM96L02 Dual Retriggerable Resetta ble Monostable Multivibrator March 199 2 96L02 DM96L02 www.datasheet4u.com Du al Retriggerable Resettable Monostable Multivibrator General Description The 9 6L02 is a dual TTL monostable multivibr ator with trigger mode selection reset capability rapid recovery internally co mpensated reference levels and high spe ed capability Output pulse duration and accuracy depend on external timing com ponents and are therefore under user co ntrol for each application It is well s uited for a broad variety of applicatio ns including pulse delay generators squ are wave generators long delay timers p ulse absence detectors frequency detect ors clock pulse generators and fixed-fr equency dividers Each input is provided with a clamp diode to limit undershoot and minimize ringing induced by fast f all times acting on system wiring imped ances Features Y Y Y Y Y Y Y Y Retrig gerable 0% to 100% duty cycle DC level triggering insensitive to transition times Leading or trailing-.

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March 1992
96L02 DM96L02
Dualwww.datasheet4u.com Retriggerable Resettable
Monostable Multivibrator
General Description
The 96L02 is a dual TTL monostable multivibrator with trig-
ger mode selection reset capability rapid recovery inter-
nally compensated reference levels and high speed capabil-
ity Output pulse duration and accuracy depend on external
timing components and are therefore under user control for
each application It is well suited for a broad variety of appli-
cations including pulse delay generators square wave gen-
erators long delay timers pulse absence detectors fre-
quency detectors clock pulse generators and fixed-frequen-
cy dividers Each input is provided with a clamp diode to
limit undershoot and minimize ringing induced by fast fall
times acting on system wiring impedances
Features
Y Retriggerable 0% to 100% duty cycle
Y DC level triggering insensitive to transition times
Y Leading or trailing-edge triggering
Y Complementary outputs with active pull-ups
Y Pulse width compensation for DVCC and DTA
Y 50 ns to % output pulse width range
Y Optional retrigger lock-out capability
Y Resettable for interrupt operations
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL F 10203 – 1
Order Number 96L02DMQB
96L02FMQB or DM96L02N
See NS Package Number J16A N16E or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
I0
I1
CD
Q
Q
CX
RX
Description
Trigger Input (Active Falling Edge)
Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
Positive Pulse Output
Complementary Pulse Output
External Capacitor Connection
External Resistor Connection
TL F 10203 – 2
C1995 National Semiconductor Corporation TL F 10203
RRD-B30M105 Printed in U S A

                 






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