96LS02 Datasheet | Dual Retriggerable Resettable Monostable Multivibrator

(Datasheet) 96LS02 Datasheet PDF Download

Part Number 96LS02
Description Dual Retriggerable Resettable Monostable Multivibrator
Manufacture Fairchild Semiconductor
Total Page 8 Pages
PDF Download Download 96LS02 Datasheet PDF

Features: 9602 DM9602 Dual Retriggerable Resettabl e One Shots June 1989 9602 DM9602 Dua l Retriggerable Resettable One Shots Ge neral Description These dual resettable retriggerable one shots have two input s per function one which is active high and one which is active low This allow s the designer to employ either leading -edge or trailing-edge triggering which is independent of input transition tim es When input conditions for triggering are met a new cycle starts and the ext ernal capacitor is allowed to rapidly d ischarge and then charge again The retr iggerable feature permits output pulse widths to be extended In fact a continu ous true output can be maintained by ha ving an input cycle time which is short er than the output cycle time The outpu t pulse may then be terminated at any t ime by applying a low logic level to th e RESET pin Retriggering may be inhibit ed by either connecting the Q output to an active high input or the Q output t o an active low input Features Y Y Y Y Y Y Y 70 ns to % outp.

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May 1992
96LS02 DM96LS02
Dual Retriggerable Resettable Monostable Multivibrator
General Description
The 96LS02 is a dual retriggerable and resettable monosta-
ble multivibrator The one-shot provides exceptionally wide
delay range pulse width stability predictable accuracy and
immunity to noise The pulse width is set by an external
resistor and capacitor Resistor values up to 1 0 MX reduce
required capacitor values Hysteresis is provided on both
trigger inputs of the 96LS02 for increased noise immunity
Y Required timing capacitance reduced by factors of 10
to 100 over conventional designs
Y Broad timing resistor range 1 0 kX to 2 0 MX
Y Output Pulse Width is variable over a 2000 1 range by
resistor control
Y Propagation delay of 35 ns
Y 0 3V hysteresis on trigger inputs
Y Output pulse width independent of duty cycle
Y 35 ns to % output pulse width range
Connection Diagram
Dual-In-Line Package
TL F 9816 – 1
Order Number 96LS02DMQB 96LS02FMQB DM96LS02M or DM96LS02N
See NS Package Number J16A M16A N16E or W16A
Pin Names
Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
True Pulse Output
Complementary Pulse Output
C1995 National Semiconductor Corporation TL F 9816
RRD-B30M115 Printed in U S A


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