Document
A29DL324 Series
32M-Bit CMOS Low Voltage Dual Operation Flash Memory
Preliminary 4M-Byte by 8-Bit (Byte Mode) / 2M-Word by 16-Bit (Word Mode)
Features
n Two bank organization enabling simultaneous execution of erase / program and read n Bank organization: 2 banks (16 Mbits + 16 Mbits) n Memory organization: - 4,194,304 words x 8 bits (BYTE mode) - 2,097,152 words x 16 bits (WORD mode) n Sector organization: 71 sectors (8 Kbytes / 4 Kwords × 8 sectors, 64 Kbytes / 32 Kwords × 63 sectors) n 2 types of sector organization - T type: Boot sector allocated to the highest address (sector) - B type: Boot sector allocated to the lowest address (sector) n 3-state output n Automatic program - Program suspend / resume n Unlock bypass program n Automatic erase - Chip erase - Sector erase (sectors can be combined freely) n Erase suspend / resume n Program / Erase completion detection - Detection through data polling and toggle bits - Detection through RY/ BY pin n Sector group protection - Any sector group can be protected - Any protected sector group can be temporary unprotected n Sectors can be used for boot application n Hardware reset and standby using RESET pin n Automatic sleep mode n Boot block sector protect by WP (ACC) pin n Conforms to common flash memory interface (CFI) n Extra One Time Protect Sector provided
Part No. Access time (Max.) Operating Power supply current Standby supply (Active mode) current voltage (Max.) (Max.)
A29DL324
90ns
2.7V~ 3.6V
16mA
30mA
5 A
n Operating ambient temperature: -40 to 85°C n Program / erase time - Program: 9.0 µs / byte (TYP.) 11.0 µs / word (TYP.) - Sector erase: 0.7 s (TYP.) n Number of program / erase: 1,000,000 times (MIN.) n Package options - 48-pin TSOP (I) or 63-ball TFBGA
General Description
The A29DL324 is a flash memory organized of 33,554,432 bits and 71 sectors. Sectors of this memory can be erased at a low voltage (2.7 to 3.6 V) supplied from a single power source, or the contents of the entire chip can be erased. Two modes of memory organization, BYTE mode (4,194,304 words × 8 bits) and WORD mode (2,097,152 words × 16 bits), are selectable so that the memory can be programmed in byte or word units. The A29DL324 can be read while its contents are being erased or programmed. The memory cell is divided into two banks. While sectors in one bank are being erased or programmed, data can be read from the other bank thanks to the simultaneous execution architecture. The banks are 8 Mbits and 24 Mbits. This flash memory comes in two types. The T type has a boot sector located at the highest address (sector) and the B type has a boot sector at the lowest address (sector). Because the A29DL324 enables the boot sector to be erased, it is ideal for storing a boot program. In addition, program code that controls the flash memory can be also stored, and the program code can be programmed or erased without the need to load it into RAM. Eight small sectors for storing parameters are provided, each of which can be erased in 8 Kbytes units. Once a program or erase command sequence has been executed, an automatic program or automatic erase function internally executes program or erase and verification automatically. Because the A29DL324 can be electrically erased or programmed by writing an instruction, data can be reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of applications.
PRELIMINARY
(May, 2002, Version 0.0)
1
AMIC Technology, Inc.
A29DL324 Series
Pin Configurations
n TSOP (I)
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET NC WP (ACC) RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O 15 (A-1) I/O 7 I/O 14 I/O 6 I/O 13 I/O 5 I/O 12 I/O 4 VCC I/O 11 I/O 3 I/O 10 I/O 2 I/O 9 I/O 1 I/O 8 I/O 0 OE GND CE A0
A29DL324V
n TFBGA
Top View Bottom View
8 7 6 5 4 3 2 1 A B C D E F G H J K L M M L K J H G F E D C B A
A 1 2 3 4 5 6 7 8 NC NC NC NC
B NC NC
C A13 A9
D A12 A8
E A14 A10 NC A18 A6 A2
Top View F A15 A11 A19 A20 A5 A1
G A16 I/O7 I/O5 I/O2 I/O0 A0
H
J
K
L NC NC
M NC NC
WE
RESET
BYTE I/O15(A-1) GND I/O14 I/O13 I/O6 I/O12 VCC I/O4
I/O10 I/O8 I/O11 I/O9 I/O3 I/O1 GND
RY/ BY WP (ACC) A7 A17 A3 A4 NC
CE
OE
NC NC
NC NC
PRELIMINARY
(May, 2002, Version 0.0)
2
AMIC Technology, Inc.
A29DL324 Series
Block Diagram
VCC GND Address Buffers Bank 2 Address Address Latch X-Decoder Cell Matrix (Bank 2)
A0-A20
Y-Decoder
Y-Gating
Bank / Sector Decoder WP(ACC) Program / Erase Voltage Generator RESET WE BYTE CE OE State Control (Command Register) SA / WC I/O 0 - I/O 15 (A-1)
Data Latch
Input / Output Buffers
SA / WC
RY/BY Address Latch
Y-Decoder
Y-Gating
Bank 1 Address
X-Decoder
Cell Matrix (Bank 1)
Pin Descriptions
Pin No. A0 - A20 I/O0 - I/O14 I/O15 I/O15 (A-1) A-1 Description Address Inputs Data Inputs/Outputs
Data Input/Output, Word Mode
LSB Ad.