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A3959 Dataheets PDF



Part Number A3959
Manufacturers Allegro MicroSystems
Logo Allegro MicroSystems
Description DMOS Full-Bridge PWM Motor Driver
Datasheet A3959 DatasheetA3959 Datasheet (PDF)

A3959 DMOS Full-Bridge PWM Motor Driver FEATURES AND BENEFITS ▪ ±3 A, 50 V Output Rating ▪ Low rDS(on) Outputs (270 mΩ, Typical) ▪ Mixed, Fast, and Slow Current-Decay Modes ▪ Synchronous Rectification for Low Power Dissipation ▪ Internal UVLO and Thermal-Shutdown Circuitry ▪ Crossover-Current Protection ▪ Internal Oscillator for Digital PWM Timing PACKAGES: Package LB, 24-pin SOIC with internally fused pins Package LP, 28-pin TSSOP with exposed thermal pad Not to scale DESCRIPTION Designed for.

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A3959 DMOS Full-Bridge PWM Motor Driver FEATURES AND BENEFITS ▪ ±3 A, 50 V Output Rating ▪ Low rDS(on) Outputs (270 mΩ, Typical) ▪ Mixed, Fast, and Slow Current-Decay Modes ▪ Synchronous Rectification for Low Power Dissipation ▪ Internal UVLO and Thermal-Shutdown Circuitry ▪ Crossover-Current Protection ▪ Internal Oscillator for Digital PWM Timing PACKAGES: Package LB, 24-pin SOIC with internally fused pins Package LP, 28-pin TSSOP with exposed thermal pad Not to scale DESCRIPTION Designed for pulse width modulated (PWM) current control of DC motors, the A3959 is capable of output currents to ±3 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be adjusted via control inputs to operate in slow, fast, and mixed current-decay modes. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM-control signals. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of supply and charge pump, and crossover-current protection. Special power-up sequencing is not required. The A3959 provides a choice of two power packages: a 24-lead SOIC with four internally fused pins (package suffix ‘LB’), and a thin (<1.2 mm) 28-pin TSSOP with an exposed thermal pad (suffix ‘LP’). In all cases, the power pins and tabs are at ground potential and need no electrical isolation. Each package is lead (Pb) free, with 100% matte tin leadframes. Functional Block Diagram VDD LOGIC SUPPLY CP1 CP2 CP VBB + LOAD SUPPLY TO VDD CHARGE PUMP BANDGAP VDD CREG TSD UNDERVOLTAGE & FAULT DETECT CHARGE PUMP BANDGAP REGULATOR VREG SLEEP EXT MODE PHASE ENABLE TO VDD BLANK PFD1 PFD2 ROSC 29319.37L, Rev. 14 MCO-0000727 CONTROL LOGIC PWM TIMER OSC GATE DRIVE ZERO CURRENT DETECT CURRENT SENSE REFERENCE BUFFER & ÷10 OUTA OUTB SENSE CS RS REF VREF Dwg. FP-048-2A October 21, 2022 A3959 DMOS Full-Bridge PWM Motor Driver SELECTION GUIDE Part Number A3959SLBTR-T A3959SLPTR-T Package 24-pin SOIC with internally fused pins 28-pin TSSOP with exposed thermal pad Packing 1000 per reel 4000 per reel ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Load Supply Voltage VBB Logic Supply Voltage VDD Input Voltage VIN Sense Voltage Reference Voltage VS VREF Output Current IOUT Package Power Dissipation PD Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) Storage Temperature Tstg Notes Rating 50 7.0 Continuous tw < 30 ns Continuous –0.3 to VDD + 0.3 –1.0 to VDD + 1.0 0.5 tw < 3 µs 2.5 VDD Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of Repetitive ±3.0 conditions, do not exceed the specified current rating or a junction temperature of 150°C. Peak, < 3 µs ±6.0 See Thermal Characteristics – Range S –2.


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